Regviz

Cypress Semiconductor /psoc63 /SCB0 /INTR_CAUSE

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as INTR_CAUSE

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Cypress Semiconductor/psoc63/SCB0/INTR_CAUSE#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (M)M0 (S)S0 (TX)TX 0 (RX)RX 0 (I2C_EC)I2C_EC 0 (SPI_EC)SPI_EC

Description

Active clocked interrupt signal

Fields

M

Master interrupt active (‘interrupt_master’): INTR_M_MASKED != 0.
S

Slave interrupt active (‘interrupt_slave’): INTR_S_MASKED != 0.
TX

Transmitter interrupt active (‘interrupt_tx’): INTR_TX_MASKED != 0.
RX

Receiver interrupt active (‘interrupt_rx’): INTR_RX_MASKED != 0.
I2C_EC

Externally clock I2C interrupt active (‘interrupt_i2c_ec’): INTR_I2C_EC_MASKED != 0.
SPI_EC

Externally clocked SPI interrupt active (‘interrupt_spi_ec’): INTR_SPI_EC_MASKED != 0.

Links

()

Register License

Copyright 2016-2018 Cypress Semiconductor Corporation \n Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License.
You may obtain a copy of the License at \n
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and
limitations under the License.

 ()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data